1. Field of Endeavor
The example embodiments encompass methods of forming non-volatile memory cells, non-volatile memory cells having particular structural characteristics and semiconductor devices incorporating such non-volatile memory cells. In particular, example embodiments include methods of forming
2. Related Art
Non-volatile memory, or non-volatile storage, is computer memory that can retain the stored information for long periods without requiring any electrical power. Examples of non-volatile memory include read-only memories, flash memories, most types of magnetic computer storage devices (e.g., hard disks, floppy disk drives, and magnetic tape) and optical storage devices (e.g., CD, DVD and Blu-ray disks). Non-volatile memories may be used as secondary storage devices, e.g., memory devices that cooperate with dynamic primary storage devices to maintain data while reducing energy requirements, particularly in portable battery-powered devices.
Currently, the most widely used form of primary storage are volatile memory devices broadly categorized as random access memory (RAM) devices, particularly dynamic random access memory (DRAM) devices. Although these volatile memory devices typically provide certain advantages over corresponding non-volatile devices, for example, with respect to processing speed or size, but typically exhibit certain fundamental disadvantages, for example, significantly higher power consumption.
Flash memories store information in an array of floating gate transistors, also referred to as “memory cells,” each of which is conventionally configured for storing one bit of information corresponding to a bistable parameter, for example, conductivity, charge or gate threshold voltage. Some newer flash memory devices, which are sometimes referred to as multi-level cell devices, are configured for storing more than 1 bit per cell and utilize a parameter that can exhibit more than two distinct levels.
In NOR flash memory devices the individual memory cells typically exhibit a transistor structure that includes a control gate (CG) much like a conventional MOS transistor and a floating gate (FG) that is isolated from surrounding conductors by a dielectric material (also referred to as an interpoly dielectric (IPD)) and is positioned between the CG and the substrate. The IPD isolates the floating gate and can be formed from any suitable dielectric material including, for example, silicon oxide or a composite material such as oxide-nitride-oxide (ONO).
Because the FG is isolated, electrons added to the FG tend to remain on the FG and will affect the electric field generated by the CG, thereby modifying the threshold voltage (Vt) of the transistor cell as illustrated graphically in FIGS. 1A and 1B. Accordingly, when the memory cell is “read” by applying a specific voltage to the CG that will result in a flow of electrical current through the transistor if the FG is sufficiently discharged or substantially no flow of electrical current through the transistor is the FG has been “programmed” and carries sufficient electrons to increase the Vt of the memory cell to a level above the voltage applied to the CG. This presence or absence of current is, in turn, sensed and transformed into a 1 or a 0, thereby allowing the data stored in the memory cell to be “read.” In multi-level cell devices, however, the magnitude of current flow will be sensed and analyzed to determine the approximate number of electrons that have been stored on the FG, thereby providing for memory states in addition to a 1 or a 0.
NOR flash memory cells may be programmed by initiating electron flow between the source and drain and then applying a sufficiently large voltage to the CG to produce a electric field sufficient to draw electrons through the insulating material surrounding the FG, a process sometimes referred to as hot-electron injection. In order to erase (for example, resetting all the memory cells to 1's in preparation for programming) a NOR flash cell, a voltage differential is established between the CG and source sufficient to induce movement of the electrons from the FG to the source through a process referred to as quantum tunneling or Fowler-Nordheim (F-N) tunneling. As will be appreciated by those skilled in the art, the performance achieved with this tunneling phenomenon depends on the properties of the materials and the configuration of the elements including, for example, cathode elements having higher aspect ratios may be utilized for producing higher field emission currents. The current density produced by a given electric field is governed by the Fowler-Nordheim equation. In single-voltage devices the high voltage needed for quantum tunneling may be generated using an on-chip charge pump.
NOR flash memory devices are typically configured in a manner that groups memory cells into erase segments, also referred to as blocks or sectors, that must be erased at the same time while still providing for programming the memory cells within such an erase segment one byte or word at a time. In contrast to NOR flash memory devices, NAND flash memory devices are typically configured to utilize quantum tunneling for both programming (writing) and erasing (reset) operations.
NOR flash memory devices and NAND flash memory devices tend to be utilized in somewhat different applications. NOR flash memory devices, for example, typically provide better random access and tend to be used more widely as code and data memory devices in applications such as BIOS/Networking (including, for example, PC, router and hub applications), telecommunications (for example, switchers), cellular phones, POS (point of sale), PDA (personal digital assistants) and PCA (program calibration array) (for example, code, call and contact data). NAND flash memory devices, however, typically provide lower cost and higher densities and tend to be used more widely as mass storage devices in applications such as memory cards (including, for example, mobile computers and USB flash drives), solid state disks (including rugged or hardened storage applications), digital cameras (including both still and moving images) and voice and/or audio recorders (providing, for example, near CD quality recordings).
As the density of flash memory devices increases, the area available for formation of the individual memory cells decreases and the number of electrons that may be loaded onto a particular floating gate also decreases. Reduced spacing between memory cells can contribute to coupling between adjacent floating gates that will affect the cell write characteristics. Various designs have, therefore, been proposed for improving the electrical isolation between adjacent memory cells at higher integration densities.
As noted above, compared with NAND flash memory devices, NOR flash memory devices tend to exhibit longer erase and write times but also provide full address/data (memory) interface that allows random access to any location within the memory cell array. This feature makes NOR flash memory devices generally more suitable for storing program code that do not need to be updated frequently, for example, a computer's BIOS (basic input/output system) or the firmware of cable and satellite “boxes” associated with television signals. Conversely, relative to NOR flash memory devices, NAND flash memory devices tend to exhibit faster erase and write times, higher density, lower cost per bit and improved endurance. NAND flash memory devices, however, typically utilize an I/O interface that provides for only sequential access to the stored data, thereby tending to slow the recovery of stored data. Accordingly, NAND flash memory devices are generally more suitable for mass-storage devices and somewhat less useful for computer memory.
Relative to hard disk drives, both NOR and NAND flash memory devices are limited in that they can provide only a finite number of erase-write cycles (although because many commercial flash memory products are designed to withstand one million programming cycles this limitation may be largely irrelevant for many applications). One technique for addressing this limitation utilizes chip firmware and/or file system drivers to count the writes to each sector and dynamically remap the blocks in order to spread the write operations more evenly between the sectors and/or by utilizing write verification and remapping to spare sectors when a write failure is detected.